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Description
This training will show you how to constrain and analyze single data rate source synchronous interfaces with the Timing Analyzer in the Intel® Quartus® Prime software. You will learn the benefits of source synchronous interfaces as compared to common clock system interfaces. You will be able to write Synopsys* Design Constraints (SDC) to constrain single data rate source synchronous inputs and outputs. You will also learn to use the Timing Analyzer to report and analyze timing for source synchronous inputs and outputs.