Altera® Hyperflex™ FPGA Architecture Design: Loop Optimization

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Intel® FPGA Development Tools Support Intel® FPGA Training Catalog Intel Agilex® 7 I-Series FPGA and SoC FPGA Support Intel Agilex® 7 M-Series FPGA and SoC FPGA Support Intel® Stratix® 10 FPGAs and SoC FPGAs Support

653045
2024-04-08
Public

Description

In the Altera® Hyperflex™ FPGA Architecture Design: Loop Optimization course, you will learn why design loops may produce timing bottlenecks in FPGA designs targeting devices built using the Hyperflex architecture, namely, Agilex™ 7, Agilex™ 5 and Stratix® 10 FPGAs. what is meant by the term “critical chain” and how it relates to your design performance. You will learn about the common loops that appear in FPGA designs. While not all design loops cause performance limitations, by the end the class, you will have a few strategies that you can employ to optimize the loops that do.

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