Introduction to the Intel® FPGA P-Tile

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Intel® FPGA Training Catalog Intel® FPGA Interface IP Resource and Documentation Collection Intel® FPGA Interface IP Resource and Documentation Collection

653001
2021-09-08
Public

Description

Intel® Agilex™ F-Series and Intel Stratix® 10 DX FPGAs are packaged with Intel’s P-Tile transceiver tile, which implements the PCI Express* Gen3 and Gen4 standards. This training is the first step in learning how to build a high-speed interface using the P-Tile. You will begin by learning about Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology that makes packaging the P-Tile with the FPGA possible. You will then be introduced to the architecture and key features of the P-Tile including endpoint, root port, and transaction layer protocol (TLP) bypass modes, port bifurcation, autonomous hard IP (HIP) mode, and Single Root IO Virtualization (SR-IOV). The functional components of the tile will be described including the PMA, PCS, and configuration registers.

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