Using High Performance Memory Interfaces in Altera 28-nm and 40-nm FPGAs

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Cyclone® V FPGAs and SoC FPGAs Support Cyclone® V FPGAs and SoC FPGAs Support Cyclone® V FPGAs and SoC FPGAs Support Cyclone® V FPGAs and SoC FPGAs Support Cyclone® V FPGAs and SoC FPGAs Support

652987
2021-09-08
Public

Description

Memory interface design for FPGAs has traditionally been a complex process. This training will highlight the ease with which high performance memory interfaces can be implemented and tested in Altera 28-nm and 40-nm devices (Stratix® IV, Stratix V, Cyclone® IV, Cyclone V, Arria® II GX, and Arria V devices) using the Quartus® II software v. 12.1. You’ll learn how to select, parameterize, and test your memory controller IP easily by following a recommended design flow. This training focuses on creating DDR-style memory interfaces using Altera’s UniPHY self-calibrating PHY block. This PHY can be used with Altera’s memory controller IP or combined with your own custom controller.

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