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Description
In the class, you will learn how to use the Intel® HLS Compiler to synthesize and verify IP components for Intel FPGAs. We will first discuss the benefits of HLS then talk about features of the Intel HLS Compiler. You will learn how to use the Intel HLS compiler to perform emulation functional debug, co-simulation with a behavioral simulator and finally integrate the generated IP within an Intel Quartus® software project. Download a PDF of the presentation and a hands-on lab exercise here: <a href="https://www.intel.com/content/www/us/en/programmable/customertraining/Videos/HLSPart1.zip">https://www.intel.com/content/www/us/en/programmable/customertraining/Videos/HLSPart1.zip</a>