Intel® Stratix® 10 SoC FPGA Technical Overview

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Intel® FPGA Training Catalog Intel® Stratix® 10 FPGAs and SoC FPGAs Support Intel® Stratix® 10 FPGAs and SoC FPGAs Support Intel® Stratix® 10 FPGAs and SoC FPGAs Support Intel® Stratix® 10 FPGAs and SoC FPGAs Support

652982
2021-09-08
Public

Description

In this training you will learn about the architecture of the Intel® Stratix® 10 SoC FPGA. You will learn about the Hard Processor System (HPS) and its contents. We begin by discussing the ARM* Cortex*-A53 MPCore*. The Cache Coherency Unit (CCU) and System MMU (SMMU) memory management blocks are explained next. The bridges between the HPS, FPGA, and SDRAM are also discussed. You will also get an overview of the embedded software ecosystem for the Intel Stratix 10 SoC including Linux, HWLIBs, and SoCEDS. Finally, the training will give an overview of the boot flow of the device, which will include an explanation of the role the Secure Device Manager (SDM) plays. *Other names and brands may be claimed as the property of others.

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