Low-Density Parity-Check (LDPC) Codes Intel® FPGA IP for 5G Systems

Description

As wireless vendors begin to deploy 5G-based technology, Low-Density Parity-Check (LDPC) codes are replacing turbo codes as the coding of choice for forward error correction. This training introduces the Intel® FPGA LDPC Codes IP cores, namely the encoder and decoder blocks . It shows the basics of how these blocks work and then describes how, when using the cores, you can verify correct operation in both the simulation and hardware environments using a core-generated reference design.