Designing with Intel® Stratix® 10, Intel Arria® 10 & Intel Cyclone® 10 GX Hard IP for PCI Express*

Description

In this class, you will learn rules that must be followed to ensure proper placement of Intel® Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 GX FPGA Hard IP for PCI Express* blocks and transceiver channels, failure of which can lead to compilation errors and possibly board re-spins. You will learn how to select the best clock resource based on location along with PCI Express lane speed and configuration. You will learn how to set up and use Configuration via Protocol (CvP) using PCI Express to configure your target FPGA over the PCI Express link. You will also learn debugging tools and techniques to employ if issues arise when bringing up your PCIe link in a system.