Intel Agilex® SoC FPGA Hard Processor System (HPS) Overview

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Intel® FPGA Training Catalog Intel Agilex® 7 F-Series FPGA and SoC FPGA Support Intel Agilex® 7 I-Series FPGA and SoC FPGA Support Intel Agilex® 7 M-Series FPGA and SoC FPGA Support Intel Agilex® 7 FPGAs and SoC FPGAs Support

652900
2021-09-08
Public

Description

In this training you will learn about the architecture of the Intel Agilex® 10 SoC FPGA. You will learn about the Hard Processor System (HPS) and its contents. We begin by discussing the ARM* Cortex*-A53 MPU (Multi-Processor Unit). The Cache Coherency Unit (CCU) and System MMU (SMMU) memory management blocks are explained next. The bridges between the HPS, FPGA, and SDRAM are also discussed. The peripherals of the HPS are discussed including: UART, I2C, DMA, Ethernet MAC, and USB.

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