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Description
This training is part 1 of 2. The Platform Designer system integration tool, formerly known as Qsys, saves design time and improves productivity by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. In this training, you'll learn how to begin the creation of a system design using the Platform Designer user interface. You'll create a new system design file and add components from the Platform Designer IP Catalog to the design. This training includes a lab exercise with instructions and files that are designed for the Intel® Quartus® Prime software, version 17.1, and the Cyclone® V GX FPGA Starter Kit from Terasic.