Design Block Reuse in the Intel® Quartus® Prime Pro Software

Description

Designing, organizing, and optimizing a single, large FPGA design can be difficult and time consuming. Projects are often divided up into smaller projects that can be worked on by separate team members, for separately testing different parts of the design, or to create reusable design blocks for use in future projects. While doing this is helpful, integrating the work of different team members or reusing parts of a previous design in other projects adds complexity. In this class, you will learn about design block reuse, the ability to partition your design and provide parts of it to other projects or integrate complete or incomplete parts into your project. You’ll see how the tools facilitate this design reuse and sharing model when working with multiple Intel Quartus Prime projects.