High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices: Implementation

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Intel® FPGA Training Catalog Intel® Stratix® 10 FPGAs and SoC FPGAs Support Intel® Stratix® 10 FPGAs and SoC FPGAs Support Intel® Stratix® 10 FPGAs and SoC FPGAs Support Intel® Stratix® 10 FPGAs and SoC FPGAs Support

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2021-09-08
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High Bandwidth Memory, or HBM, is the next generation of high-speed memory built into Intel® Stratix® 10 MX FPGA devices using System in Package (SiP) technology. HBM2 enables the highest levels of bandwidth not feasible with other solutions. Multiple DRAM layers are connected to a base I/O layer to form a 3D, high-speed memory connected to and controlled directly by hard memory controllers built into the Intel Stratix 10 MX device. Integrating HBM directly in the FPGA package reduces board size and cost, simplifies and reduces power requirements, and makes it easy to add to your Intel Quartus® Prime Pro Edition project. This final part discusses how to implement HBM in the Intel Quartus® Prime software and use tools to simulate functionality and measure the efficiency of the interface.

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High Bandwidth Memory, or HBM, is the next generation of high-speed memory built into Intel® Stratix® 10 MX FPGA devices using System in Package (SiP) technology. HBM2 enables the highest levels of bandwidth not feasible with other solutions. Multiple DRAM layers are connected to a base I/O layer to form a 3-D, high-speed memory connected to and controlled directly by hard memory controllers built into the Intel Stratix 10 MX device. Integrating HBM directly in the FPGA package reduces board size and cost, simplifies and reduces power requirements, and makes it easy to add to your Intel Quartus® Prime Pro Edition project. This part of the training is an introduction to HBM and its architectural implementation in Intel Stratix 10 MX devices.
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High Bandwidth Memory, or HBM, is the next generation of high-speed memory built into Intel® Stratix® 10 MX FPGA devices using System in Package (SiP) technology. HBM2 enables the highest levels of bandwidth not feasible with other solutions. Multiple DRAM layers are connected to a base I/O layer to form a 3-D, high-speed memory connected to and controlled directly by hard memory controllers built into the Intel Stratix 10 MX device. Integrating HBM directly in the FPGA package reduces board size and cost, simplifies and reduces power requirements, and makes it easy to add to your Intel Quartus® Prime Pro Edition project. This part of the training focuses on the HBM controller (HBMC) and the Arm AMBA 4 AXI interface to the controller from the user logic.
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