Chip ID Reading Using Mailbox Avalon® ST Client Intel® FPGA IP in Intel® Agilex™ FPGAs

Download

Intel® FPGA Quick Videos Agilex™ 7 M-Series FPGA and SoC FPGA Support Agilex™ 7 I-Series FPGA and SoC FPGA Support Agilex™ 7 F-Series FPGA and SoC FPGA Support Agilex™ 7 FPGAs and SoC FPGAs Support

649142
2020-12-09
Public

Description

This video shows the method to perform chip ID reading by interfacing with AVST interface using Mailbox Avalon® ST Client Intel® FPGA IP in Intel® Agilex™ FPGA. For more information about Mailbox Avalon ST Client Intel® FPGA IP please refer to user guide at link below: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-avst-client-ag.pdf

Usage instructions