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Description
This whitepaper describes Intel® Transactional Synchronization Extension (Intel® TSX) and Performance Monitoring Unit (PMU) behavior due to the updated microcode for Intel® Xeon® Processor E3 v5 and v6 Family (code name Skylake, Kaby Lake), Intel® Xeon® D (code name Skylake-D), Intel® Xeon® Scalable Processor and 6th, 7th, and 8th Generation Intel® Core™ i7 and i5 (code name Skylake, Kaby Lake, Coffee Lake and Whiskey Lake).