Hard Floating Point

DSP Floating Point

New digital signal processing (DSP) systems use floating-point solutions to achieve a high degree of numeric stability and dynamic range. Applications such as radar, advanced wireless antenna processing and medical imaging require floating-point capabilities in FPGAs and SoCs. As DSP applications grow in size and capability, FPGAs and SoCs offer the highest performing platforms available for any floating-point DSP implementation.

At 14 nm, Intel® Stratix® 10 FPGAs and SoCs deliver the industry's highest floating-point performance with up to 10 tera floating point operations per second (TFLOPS) performance. Find out more about our Stratix 10 FGPA and SoC DSP capabilities.

At 20 nm, Intel® Arria® 10 FPGAs and SoCs deliver the industry’s first devices with hardened floating-point operators delivering up to 1.5 TFLOPs performance. Find out more about our Arria 10 FPGA and SoC variable-precision DSP block architecture.

Latest News: New Support for Intel® SoC FPGAs (and associated floating-point implementation) with the Latest MathWorks R2014b Release

HDL Coder and Embedded Coder offer new support for the Intel® SoC FPGA family with MathWorks R2014b. Developers familiar with MathWorks tools have the added convenience of staying in this development environment for code generation targeted for Intel SoC FPGAs.

FPGA designers and processor programmers will now share a common design methodology streamlined for targeting of Intel SoC FPGAs.

For further information, visit https://www.mathworks.com/hardware-support/altera-soc-ecoder.html.

Get started on our floating-point DSP solutions with these white papers and webcasts.

Webcasts

NEW: View now, On-Demand, 15 minutes

Accelerating Design Development Time with Hard Floating-Point DSP Blocks in FPGAs

Watch this webcast to get:

  • An overview of current floating-point implementation challenges
  • An introduction to Intel's hard floating-point DSP blocks
  • An overview of how you can achieve unprecedented DSP performance, designer productivity, and logic efficiency