Type: Answers

Area: Component



Why does my design have timing violations when using the ALTLVDS megafunction at data rates within the device specification?

Description

When using dedicated SERDES through the ALTLVDS megafunction in Altera® devices, the supported data rates are shown in the High-Speed I/O Specifications of the respective device datasheet.  However, these data rates are based on the fast clock maximum frequency which is routed on dedicated clock networks within the device.

The maximum frequency on the parallel clock domain is design dependent.  Factors that determine the parallel clock domain maximum frequency are: 

  • Data rate
  • Serialization or deserialization factor
  • Device speed grade
  • Parallel domain clock network 

Timing violations can occur on the parallel (also referred to as slow clock) domain, particularly on the parallel to serial clock domain transfer.

Workaround/Fix

The serialization and deserialization factor will determine the parallel data rate with respect to the serial data rate. Assuming you cannot change the serial data rate for your system, you can reduce the parallel data rate by increasing the serialization factor for transmitters and deserialization factor for receivers. 

If changing the serialization or deserialization factor is not an option for your system, you can use a faster speed grade device to help meet your timing requirements.

You can also improve the parallel clock domain timing by selecting Regional or Dual-Regional routing resources for the tx_coreclock in the ALTLVDS_TX megafunction, or for the rx_outclock in the ALTLVDS_RX megafunction.  The Quartus® II software may select global routing resources by default.  When using high performance I/O interfaces, regional clock networks can provide better timing results.

If the fanout for the tx_coreclock or rx_outclock in your design requires global resources, you can add the ALTCLKCTRL megafunction to your design and connect its inclk port to the rx_outclock or tx_coreclock output port.  Connect the outclk port of the ALTCLKCTRL megafunction to the core fanout.  The ALTLVDS auto-generated registers will still use a regional clock network per the selection in the ALTLVDS megafunction while your remaining logic will use the global resource that you select in the ALTCLKCTRL megafunction. 

If you are using ALTLVDS with the external PLL mode option, you should add two ALTCLKCTRL megafunctions to the design.  One should be set up as a regional clock used for the registers being driven by the ALTLVDS_RX rx_out port, or the registers driving the ALTLVDS_TX tx_in port.  The other ALTCLKCTRL megafunction should be set up as a global clock which drives the remaining logic using the rx_outclock or tx_coreclock

You can verify your design is using both types of clock networks for the rx_outclock and tx_coreclock by viewing Global & Other Fast Signals in the Compilation Report.