Article ID: 000080975 Content Type: Troubleshooting Last Reviewed: 10/15/2012

Why does the PCIe Hard IP endpoint not return MSI interrupt message app_msi_ack back to the rootport after app_msi_req is asserted?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

To correctlt enable MSI interrupts, the host must first set the MSI Enable bit, then set the Interrupt Disable bit and finially set the Bus Master bit, as described in the steps below:

1. Set the MSI Enable at bit[0] of MSI Control Status register, this bit is mapped to bit[16] of configuration space register offset 0x50.

2. Set the Interrupt Disable at bit[10] of Command Register at configuration space offset register 0x4 to disable legacy interrupt.

3. Set the Bus Master at bit[2] of Command Register at configuration space offset register 0x4 to enable the ability to generate MSI message.

Related Products

This article applies to 4 products

Arria® II GX FPGA
Arria® II GZ FPGA
Cyclone® IV GX FPGA
Stratix® IV GX FPGA