Description
When using the Intel® Arria® 10 PCIe Hard IP in CvP or Autonomous mode, it is a requirement that the PCIe reference clock is either stable from power up or stable from the point it is enabled prior to the release of the nPERST#.
The PCIe reference clock must not be unstable during the PCIe Hard IP phase-locked loop (PLL) or transceiver calibration phase.
Resolution
It is not possible to instigate a user mode re-calibration of the transceivers if this happens.