Type: Answers

Area: Embedded

Last Modified: March 22, 2017
Version Found: v16.0
Bug ID: FB: 414148;
IP: Qsys Interconnect, AXI Translator, APB Translator, Avalon-MM Slave Translator, Avalon-MM Master Translator

Can I manually instantiate Qsys Translator IP in a Qsys system?


Due to a problem in the Quartus® Prime software version 16.1 and earlier AXI, Avalon MM and APB Translator IPs are visible in the Quartus Prime software Qsys IP Catalog window under Qsys Interconnect / Memory-Mapped section.

Translator IPs should not be manually added to Qsys systems,  Qsys will add them automatically to generate system interconnect.  


This problem is due to be fixed in a future version of the Quartus Prime software.