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• 3-D and III-V Transistors

3-D and III-V Transistors

In 2002, Intel announced that it had developed a novel three-dimensional design that will allow the manufacture of transistors that scale, perform, and address the current leakage problem seen in two-dimensional planar transistors. Tri-gate fully-depleted substrate transistors have a raised plateau-like gate structure with two vertical walls and a horizontal wall of gate electrode. This three-dimensional structure improves the drive current while the depleted substrate reduces the leakage current when the transistor is in the "off" state. Reducing leakage current not only helps control heat at the circuit level but also translates to increased battery life in mobile devices.

Intel's tri-gate technology surrounds the channel on three of four sides, making it significantly more power efficient than either planar or FinFET transistor technology (an alternative 3-D architecture that has been proposed by IBM and others). The efficiency of the tri-gate design is then enhanced by using both high-k gate insulators with metal gates to improve both on and off currents, and adding strained silicon for enhanced mobility (speed), further improving device performance.

In June 2006, Intel researchers announced the development of improved CMOS tri-gate (3D) transistors, which are the first to integrate high-k gate dielectrics and strained silicon to produce record drive currents and transistor efficiency.

Learn more

Integrated CMOS Tri-Gate Transistors
Continuing transistor performance and scaling trends while controlling parasitic leakages

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

 

Intel and QinectQ

In December 2005, researchers at Intel and QinetiQ announced the development of a new, ultra-fast, yet very low power prototype transistor using indium antimonide (chemical symbol: InSb) that could form the basis of microprocessors and other logic products beginning in the second half of the next decade. The prototype transistor is much faster and consumes less power than previously announced transistors.

Intel press release

85nm Gate Length Enhancement and Depletion mode InSb Quantum Well Transistors for Ultra High Speed and Very Low Power Digital Logic Applications

Previous press release on Intel's work with (QinetiQ)

of Intel's activities in nanotechnology from Intel fellow Robert Chau that appeared in the May 2005 issue of Nanotech Briefs.

You can also explore the following presentations and publication links to learn more about our transistor and nanotechnologies.

Presentations

Event: IEDM 2008
Author: Robert Chau

Heterogeneous Integration of Enhancement Mode In0.7Ga0.3As Quantum Well Transistor on Silicon Substrate using Thin (<2 mm) Composite Buffer Architecture for High-Speed and Low-voltage (0.5V) Logic Applications

Technical Paper
Presenter: Mantu Hudait
Event: 2007 International Electron Devices Meeting (IEDM)
Date: December 11, 2007

Presenter: Robert Chau
Event: Keynote presentation at the 8th International Conference on Solid-State and Integrated Circuits Technology (ICSICT)
Date: October 23-26, 2006
Shanghai, China

Presenter: Robert Chau
Event: Device Research Conference (DRC 2006), plenary presentation
Date: June 26, 2006

InSb Quantum Well Transistors

Technical Paper
Presenter: S. Datta
Co-Authors: S. Datta, T. Ashley¹, J. Brask, L. Buckle¹, M. Doczy, M. Emeny¹, D. Hayes¹, K. Hilton¹, R. Jefferies¹, T. Martin¹, T. J. Phillips¹, D. Wallis¹, P. Wilding¹ and R. Chau
(¹QinetiQ, QinetiQ Malvern Technology Center, Malvern, UK)
Event: 2005 IEEE International Electron Devices Meeting (IEDM)
Date: December 5–7, 2005

Presenter: Robert Chau
Event: Plenary talk, 14th Biennial Conference on Insulating Films on Semiconductors 2005 (INFOS 2005), Leuven, Belgium
Date: June 22-24, 2005

Presenter: Robert Chau
Event: (2005 IEEE VLSI-TSA International Symposium on VLSI Technology), Hsinchu, Taiwan
Date: April 25-27, 2005

"Novel InSb-based Quantum Well Transistors for Ultra-High Speed, Low Power Logic Applications"

Presenter: S. Datta and Robert Chau
Co-Authors: T. Ashley, A. R. Barnes, L. Buckle, A. B. Dean, M. T. Emeny, M. Fearn, D. G. Hayes, K. P. Hilton, R. Jefferies, T. Martin, K. J. Nash, T. J. Phillips, W. H. A. Tang and P. J. Wilding
Event: The 7th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2004
Date: October 20, 2004

Publications

G. Dewey, M. Hudait, K. Lee, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit and Robert Chau IEEE Electron Device Letters, Vol. 29, No. 10, pp. 1094-1087, October 2008

Doyle, B.S.; Datta, S.; Doczy, M.; Hareland, S.; Jin, B.; Kavalieros, J.; Linton, T.; Murthy, A.; Rios, R.; Chau, R.;
Electron Device Letters, IEEE Volume 24, Issue 4, April 2003 Page(s):263 - 265

Doyle, B.; Boyanov, B.; Datta, S.; Doczy, M.; Hareland, S.; Jin, B.; Kavalieros, J.; Linton, T.; Rios, R.; Chau, R.;
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on 10-12 June 2003 Page(s):133 - 134

R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani, and S. Datta
Ext. Abst. 2002 Int. Conf. Solid State Devices & Materials, Nagoya, Japan, pp. 68-69.

Opportunities and Challenges of III-V Nanoelectronics for Future High-speed, Low-power Logic Applications
Authors: Robert Chau, Suman Datta, Amlan Majumdar
Event/Publication: Technical Digest, IEEE Compound Semiconductor Integrated Circuit
Symposium (2005 IEEE CSICS), Palm Springs, CA., Nov. 2005, pp. 17-20.

Emerging Silicon and Non-Silicon Nanoelectronic Devices: Opportunities and Challenges for Future High-Performance and Low-Power Computational Applications
Authors: Robert Chau, Justin Brask, Suman Datta, Gilbert Dewey, Mark Doczy, Brian Doyle, Jack Kavalieros, Ben Jin, Matthew Metz, Amlan Majumdar, and Marko Radosavljevic
Event/Publication: (2005 IEEE VLSI-TSA International Symposium on VLSI Technology), April 25-27, 2005, Hsinchu, Taiwan, Proceedings of Technical Papers, Pages 13-16

Authors: Robert Chau, Datta, S., Doczy, M., Doyle, B., Jin, B., Kavalieros, J., Majumdar, A., Metz, M. and Radosavljevic, M.
Publication: IEEE Transactions on Nanotechnology, Vol. 4, No. 2, pp. 153-158, March 2005

Authors: Robert Chau, Mark Doczy, Brian Doyle, Suman Datta, Gilbert Dewey, Jack Kavalieros, Ben Jin, Matthew Metz, Amlan Majumdar and Marko Radosavljevic
Publication: Proceedings of the 7th International Conference on Solid State and Integrated Circuit Technology
(ICSICT 2004) in Beijing, China, pp. 26-30