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Intel® Developer Network for PCI Express* Architecture Resources

Specifications

  • PHY Interface for the PCI Express* (PIPE) Architecture Gen 3 Revision 0.5

    File Type/Size:  PDF 270KB

    This document is a draft version of the PIPE spec that supports PCI Express* Gen 3. The PIPE spec (PHY Interface for PCI Express* Architecture) describes a standardized interface between PCIe MAC implementations and PCIe PHY implementations. By downloading and reading the spec you agree to the obligations set forth in the Intel® Developer Network for PCI* Express Architecture user agreement. Comments can be sent to admin@pciexpressdevnet.org.

  • PHY Interface for the PCI Express* (PIPE) Architecture Gen 2 Revision 2.0

    File Type/Size:  PDF 243KB

    This document is a final version of the PIPE spec that supports PCI Express* Gen 2. The PIPE spec (PHY Interface for PCI Express* Architecture) describes a standardized interface between PCIe MAC implementations and PCIe PHY implementations. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.

  • MAC-PHY Interface Connector for PCI Express* (PIPE) Architecture

    File Type/Size:  PDF 397KB

    August 19, 2005
    This document describes a standardized connector interface for discrete PHYs. The connector can handle PHYs with up to four lanes. The design is intended for prototyping/testing work, allowing MAC developers to be able to easily connect to PHYs from different vendors, and similarly provide an easy way for PHY vendors to try their designs with multiple MAC vendors.

  • PHY Interface for the PCI Express* Rev. 1.1 (PIPE) Architecture

    File Type/Size:  PDF 373KB

    June 16, 2003
    This document describes a standardized interface between PCIe MAC implementations and PCIe PHY implementations. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.

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