Product Features Datasheet ■ PCI Bus — PCI revision 2.3, 32-bit, 33/66 MHz — Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands — 3.3 V (5 V tolerant PCI signaling) ■ MAC Specific — Low-latency transmit and receive queues — IEEE 802.3x-compliant flow-control support with software-controllable thresholds — Caches up to 64 packet descriptors in a single burst — Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B) — Wide, optimized internal data path architecture — 64 KB configurable Transmit and Receive FIFO buffers ■ PHY Specific — Integrated for 10/100/1000 Mb/s operation — IEEE 802.3ab Auto-Negotiation support — IEEE 802.3ab PHY compliance and compatibility — State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation — Automatic polarity detection — Automatic detection of cable lengths and MDI vs. MDI-X cable at all speeds ■ Host Off-Loading — Transmit and receive IP, TCP, and UDP checksum off-loading capabilities — Transmit TCP segmentation — Advanced packed filtering — Jumbo frame support up to 16 KB — Intelligent Interrupt generation (multiple packets per interrupt) ■ Manageabiltiy — Network Device Class Power Management Specification 1.1 — Compliance with PCI Power Management 1.1 and ACPI 2.0 —SNMP and RMON statistic counters — D0 and D3 power states ■ Additional Device — Four programmable LED outputs — On-chip power control circuitry — BIOS LAN Disable pin — JTAG (IEEE 1149.1) Test Access Port built in silicon (3.3 V, 5 V tolerant PCI signaling) a ■ Lead-free 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: LUxxxxxx. a. This device is lead-free. That is, lead has not been <1000 ppm. The Material Declaration Data Sheet, which Restriction on Hazardous Substances (RoHS)-banned In addition, this device has been tested and conforms to the the device. For more information regarding lead-free products from tative intentionally added, but lead may still exist as an impurity at includes lead impurity levels and the concentration of other materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks same parametric specifications as previous versions of Intel Corporation, contact your Intel Field Sales represen- 318139-002 Revision 4.3 Revision History Date Aug 2003 Mar 2004 Oct 2004 Nov 2004 Jan 2005 Feb 2005 Apr 2005 July 2005 Aug 2005 June 2006 June 2006 Aug 2006 Sept 2006 Aug 2007 June 2008 Revision 2.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 Notes Non-classified release. Updated Section 4, “Voltage, Temperature, and Timing Specifications,” for the C-0 stepping. • Corrected EEMODE signal description. • Updated signal names to match design guide and reference schematics. • Added lead free information. • Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information. • Added statement that no changes to existing soldering processes are needed for the 2-layer 0.32 mm wide-trace substrate change in the Read the full 82541ER Gigabit Ethernet Controller Networking Silicon.