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Strained Germanium QWFE Transistor as P-Channel Device Option for Low Power III-V CMOS Architecture

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Strained Germanium QWFE Transistor as P-Channel Device Option for Low Power III-V CMOS Architecture

In this article we demonstrate a Ge p-channel QWFET with scaled TOXE = 14.5Å and mobility of 770 cm2/V*s at ns =5x1012 cm-2 (charge density in the state-of-the-art Si transistor channel at Vcc = 0.5V). For thin TOXE < 40 Å, this represents the highest hole mobility reported for any Ge device and is 4x higher than state-of-the-art strained silicon. The QWFET architecture achieves high mobility by incorporating biaxial strain and eliminating dopant impurity scattering. The thin TOXE was achieved using a Si cap and a low Dt transistor process, which has a low oxide interface Dit. Parallel conduction in the SiGe buffer was suppressed using a phosphorus junction layer, allowing healthy sub threshold slope in Ge QWFET for the first time. The Ge QWFET achieves an intrinsic Gmsat which is 2x higher than the InSb p-channel QWFET. These results suggest the Ge QWFET is a viable p-channel option for non-silicon CMOS.

Introduction

Recently, III-V quantum well field effect transistor (QWFET) research for future low power CMOS logic applications has made significant progress [1,3]. While n-channel III-V studies have shown significant drive current gains over state of the art silicon at low Vcc [1], the corresponding p-channel transistor with thin TOXE and high mobility (µ) has not yet been demonstrated. In this study, we demonstrate a high mobility strained germanium (Ge) p-channel QWFET suitable for low power CMOS architecture with scaled TOXE = 14.5Å and hole mobility = 770 cm2/V*s at ns =5x1012 cm-2. For TOXE < 40 Å, this represents the highest hole mobility reported for any Ge device and is 4x higher than state-of-the-art strained silicon. These results suggest that the Ge QWFET is a viable p-channel option for III-V CMOS realization.

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