Registers Overview and Configuration Process
The Intel® Xeon® processor E5 v3 product family contains one or more PCI devices within each individual functional block. The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket.
Some features are only supported on specific SKU's. In such case the respective registers would only apply to the specific SKU which contains the feature support.
Refer to the Intel® Xeon® Processor E5 v3 Product Families Uncore Performance Monitoring Reference Manual for details on Performance Monitoring Registers.
Platform Configuration Structure
The DMI2 physically connects the processor and the PCH. From a configuration standpoint the DMI2 is a logical extension of PCI Bus 0. DMI2 and the internal devices in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software. As a result, all devices internal to the processor and the PCH appear to be on PCI Bus 0.
Processor IIO Devices (CPUBUSNO (0))
The processor IIO contains PCI devices within a single, physical component. The configuration registers for the devices are mapped as devices residing on PCI Bus "CPUBUSNO(0)" where CPUBUSNO(0) is programmable by BIOS.