PHY Interface for the PCI Express* and USB SuperSpeed Architectures
The PCI Express* and USB SuperSpeed PHY Interface Specification has definitions of all functional blocks and signals. This revision includes support for PCI Express implementations conforming to the PCI Express Base Specification, Revision 2.0 and implementations conforming to the Universal Serial Bus Specification, Revision 3.0.
The PHY Interface for the PCI Express and USB SuperSpeed Architectures (PIPE) is intended to enable the development of functionally equivalent PCI Express and USB SuperSpeed PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions which must be incorporated in a PIPE compliant PHY, and it defines a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is defined to allow various approaches to be used. Where possible the PIPE specification references the PCI Express base specification or USB 3.0 Specification rather than repeating its content. In case of conflicts, the PCI-Express Base Specification and USB 3.0 Specification shall supersede the PIPE spec. This spec provides some information about how the MAC could use the PIPE interface for various LTSSM states and Link states. This information should be viewed as ‘guidelines for’ or as ‘one way to implement’ base specification requirements. MAC implementations are free to do things in other ways as long as they meet the corresponding specification requirements.
One of the intents of the PIPE specification is to accelerate PCI Express endpoint and USB SuperSpeed device development. This document defines an interface to which ASIC and endpoint device vendors can develop. Peripheral and IP vendors will be able to develop and validate their designs, insulated from the high-speed and analog circuitry issues associated with the PCI Express or USB SuperSpeed PHY interfaces, thus minimizing the time and risk of their development cycles.
Read the full PHY Interface for the PCI Express* Revision.
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PHY Interface for the PCI Express* and USB SuperSpeed Architectures
The PCI Express* and USB SuperSpeed PHY Interface Specification has definitions of all functional blocks and signals. This revision includes support for PCI Express implementations conforming to the PCI Express Base Specification, Revision 2.0 and implementations conforming to the Universal Serial Bus Specification, Revision 3.0.
The PHY Interface for the PCI Express and USB SuperSpeed Architectures (PIPE) is intended to enable the development of functionally equivalent PCI Express and USB SuperSpeed PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in ASIC designs. The specification defines a set of PHY functions which must be incorporated in a PIPE compliant PHY, and it defines a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. It is not the intent of this specification to define the internal architecture or design of a compliant PHY chip or macrocell. The PIPE specification is defined to allow various approaches to be used. Where possible the PIPE specification references the PCI Express base specification or USB 3.0 Specification rather than repeating its content. In case of conflicts, the PCI-Express Base Specification and USB 3.0 Specification shall supersede the PIPE spec. This spec provides some information about how the MAC could use the PIPE interface for various LTSSM states and Link states. This information should be viewed as ‘guidelines for’ or as ‘one way to implement’ base specification requirements. MAC implementations are free to do things in other ways as long as they meet the corresponding specification requirements.
One of the intents of the PIPE specification is to accelerate PCI Express endpoint and USB SuperSpeed device development. This document defines an interface to which ASIC and endpoint device vendors can develop. Peripheral and IP vendors will be able to develop and validate their designs, insulated from the high-speed and analog circuitry issues associated with the PCI Express or USB SuperSpeed PHY interfaces, thus minimizing the time and risk of their development cycles.
Read the full PHY Interface for the PCI Express* Revision.
