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82562GT/82562GZ/82562GX/82562G LAN on Motherboard Design Guide Application Note (AP-468)

Intel® 82562ET/EM, 82562G/GT: Application Note 414

Introduction

The 82562G/GT and 82562ET/EM are highly-integrated devices designed for 10 or 100 Mbps Ethernet systems. They are based on IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. They are also 3.3 V devices available in a 48-pin Shrink Small Outline Package (SSOP).

The 82562G/GT and 82562ET/EM comply with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full Duplex Flow Control standard. The 82562G/GT and 82562ET/EM also include a PHY interface compliant to the current platform LAN connect interface.

Scope

This application note provides guidelines for system designs based on the Intel® 82562G/GT and 82562ET/EM Platform LAN Connect (PLC) devices.

The table in Section 5.0 lists the pinout assignments for each of the PLC devices. For other necessary design collateral, please refer to “Reference Documents” (Section 1.3).

Read the full Intel® 82562ET/EM, 82562G/GT application note.

Intel® 82562ET/EM, 82562G/GT: Application Note 414

Introduction

The 82562G/GT and 82562ET/EM are highly-integrated devices designed for 10 or 100 Mbps Ethernet systems. They are based on IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. They are also 3.3 V devices available in a 48-pin Shrink Small Outline Package (SSOP).

The 82562G/GT and 82562ET/EM comply with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full Duplex Flow Control standard. The 82562G/GT and 82562ET/EM also include a PHY interface compliant to the current platform LAN connect interface.

Scope

This application note provides guidelines for system designs based on the Intel® 82562G/GT and 82562ET/EM Platform LAN Connect (PLC) devices.

The table in Section 5.0 lists the pinout assignments for each of the PLC devices. For other necessary design collateral, please refer to “Reference Documents” (Section 1.3).

Read the full Intel® 82562ET/EM, 82562G/GT application note.

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