Basic Information
- Wikipedia* Article About Intel® TSX
- Blog: Transactional Synchronization with the 4th Generation Intel® Core™ processor (formerly code named Haswell)
- Blog: Coarse-grained Locks and Transactional Synchronization Explained
- Intel Developer Forum 2012 Presentation on Intel TSX (Session ARCS004)
- Going Under the Hood with the 4th Generation Intel Core processor (formerly code named Haswell)
Intel TSX Manuals
- See the chapter titled Programming with Intel® Transactional Synchronization Extensions of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1
- Intel® 64 and IA-32 Architectures Optimization Reference Manual (Chapter 12)
Lock Enabling and Tuning Intel TSX
- Blog: Using HLE and RTM with Older Compilers with TSX-tools
- Blog, how to debug and print(f) from Intel TSX: Debug Intel® Transactional Synchronization Extensions
- Presentation: Adding Lock Elision to Linux*
- Blog: Intel TSX Fallback Paths
- Article: Intel TSX Anti Patterns in Lock Elision Code
- Presentation: Making the Most of Intel® Transactional Synchronisation Extensions
- Scaling Existing Lock-based Applications with Lock Elision
Lock Implementations with Intel TSX Support
- Article: Lock Elision in the GNU C Library "pthreads" and the Source Code. (In the glibc mainline since version 2.18)
- speculative_spin_rw_mutex in Intel® Threading Building Blocks (Intel® TBB) (Article)
- speculative_spin_mutex in Intel® TBB (Article)
- OpenMP* (Since Composer XE 2013 SP1) Adaptive Lock
- Paper, with details on Intel TSX support in Intel OpenMP*: "A User-Guided Locking API for the OpenMP* Application Program Interface"
- Blog: Exploring Intel Transactional Synchronization Extensions with Intel® Software Development Emulator (Intel® SDE)
- Article: Intel TSX Anti Patterns in Lock Elision Code
- Article: Pitfalls of Lazy Subscription
Intel TSX Monitoring and Profiling
- Blog: Intel TSX Profiling with Linux* Perf
- Blog: Monitoring Intel Transactional Synchronization Extensions with Intel® PCM
- Profiling Intel® Transactional Synchronization Extensions with Intel® VTune™ Profiler
- Blog: Exploring Intel® Transactional Synchronization Extensions with Intel® SDE
- Article: Analyzing Intel SDE, Intel TSX-related Log Data For Capacity Aborts
Scientific Papers and Studies with Intel TSX
Data Structures
- Improving In-Memory Database Index Performance with Intel Transactional Synchronization Extensions, Slides
- Concurrent Hash Tables: Fast and General?
- Algorithmic improvements For Fast concurrent Cuckoo Hashing
- Radix trees: The ART of Practical Synchronization
- Empirical Evaluation of a Thread-Safe Dynamic Range Min-Max Tree using HTM
- Performance Analysis of Concurrent Red-Black Trees on HTM Platforms
- Massively Concurrent Red-Black Trees with Hardware Transactional Memory
- Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps
- A Case Study in Optimizing HTM-Enabled Dynamic Data Structures: Patricia Tries
Databases
- Exploiting Hardware Transactional Memory in Main-Memory Databases
- Using Restricted Transactional Memory to Build a Scalable In-Memory Database
- Scaling HTM-Supported Database Transactions to Many Cores
- Locality-Adaptive Parallel Hash Joins Using Hardware Transactional Memory
Memory Management
- SuperMalloc: A Super Fast Multithreaded Malloc for 64-bit Machines
- StackTrack: An Automated Transactional Approach to Concurrent Memory Reclamation
- The Influence of Malloc Placement on TSX Hardware Transactional Memory
- Chihuahua: A Concurrent, Moving, Garbage Collector using Transactional Memory
- Transactional Pointers: Experiences with HTM-Based Reference Counting in C++
Loop Speculation with Intel TSX
Thread-level Speculation on Off-the-shelf Hardware Transactional Memory
Other
- Performance Evaluation of Intel Transactional Synchronization Extensions for High-Performance Computing
- Early Experience on Transactional Execution of Java* Programs Using Intel TSX
- Accelerating Precise Race Detection Using Commercially-Available Hardware Transactional Memory Support
- Eliminating Global Interpreter Locks in Ruby Through Hardware Transactional Memory
- Adaptive Mutex Algorithm: Self-Tuning Intel Transactional Synchronization Extensions
- Kernel big lock scalability: For a Microkernel, a Big Lock Is Fine
- Simplifying Concurrent Algorithms by Exploiting Hardware Transactional Memory
- Using Hardware Transactional Memory to Enable Speculative Trace Optimization
- Literature Survey For Practical TSX Lock Elision Applications