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Intel E8500 Chipset North Bridge Datasheet

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Intel E8500 Chipset North Bridge Datasheet

The Intel® E8500 chipset is a 4-way server chipset. The chipset is built architecturally around the Intel® E8500 chipset North Bridge (NB) and the Intel® E8500 chipset eXternal Memory Bridge (XMB).

This document, the Intel® E8500 Chipset North Bridge (NB) Datasheet, describes the features, modes and registers supported by the Intel® E8500 chipset North Bridge (NB) component only. Additional details on the Intel® E8500 chipset eXternal Memory Bridge (XMB) are described in a separate document, the Intel® E8500 Chipset eXternal Memory Bridge (XMB) Datasheet. For details on any other platform component, please refer to the component’s respective documentation. This chapter is an introduction to the entire platform.

Intel® E8500 Chipset North Bridge (NB) feature list
The NB is the center of the Intel® E8500 chipset architecture (refer to Figure 1-1). The NB provides the interconnect to:
• 64-bit Intel® Xeon™ processor MP via two 667 MHz front side buses optimized for server applications XMBs via four Independent Memory Interfaces (IMI)
• I/O components via one x4 & three x8 PCI Express* links and Intel® 82801EB I/O Controller Hub 5 (ICH5) via the HI 1.5

Processor front side Bus support
• Supports up to 4, 64-bit Intel® Xeon™ processor MP
• 667 MHz operation
• Maintains coherency across both buses
• Double-pumped 40-bit address buses with ADS every other clock which provides a total address bandwidth of 167 million addresses/second
• Quad-pumped, 64-bit data bus providing a bandwidth of 5.3 GB/s per bus
• In-Order-Queue depth of 12
• Maintains coherency across both buses

Read the full Intel® E8500 Chipset North Bridge Datasheet.