Intel® 82870P2 PCI/PCI-X 64-bit Hub 2: Spec Update

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Intel® 82870P2 PCI/PCI-X 64-bit Hub 2: Spec Update

Specification Update: Intel® 82870P2 PCI/PCI-X 64-bit Hub 2

This document is an update to the specifications contained in the Affected Documents/Related Documents table. This document is a compilation of device and documentation errata, and specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published.

The table indicates the errata, specification changes, specification clarifications, or documentation changes that apply to the Intel® 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2). Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.

Split Completion Message for Inbound Dword Read has Incorrect Remaining Address Field

Problem: P64H2 does not set the lower address field to zero for a split completion message in response to DWord read request. This violates section 2.10.6 of PCI-X specification, which states that the lower address field in the Split Completion address should be set to zero.

Implication: Sensitivity to this spec violation would only occur in a P64H2 platform if a read request was sent to a device over the Hub Interface by the P64H2, and the device responded with a master/target abort. Under normal system operation, the MCH and the SIOH devices will not return a master/target abort; therefore, this spec violation will not affect the operation of the P64H2.

Workaround: None.

Status: No fix.

Read the full Intel® 82870P2 PCI/PCI-X 64-bit Hub 2 Specification Update.