The following examples provide instructions for implementing functions using tool command language (Tcl). For more information on Tcl, refer to Quartus II Help and to the Tcl Scripting chapter of the Quartus II Handbook. These Tcl examples are intended for Quartus II software version 3.0 and later.
Tcl examples for Mentor Graphics® ModelSim* and ModelSim*-Altera® simulator software are available in ModelSim* Tcl Scripting Examples.
Working with Projects and Assignments
Almost every script opens a project. See examples of how to specify project and revision names as command-line arguments when you run scripts, and learn how to open projects efficiently.
If you use the Logic Lock Region design flow, it is sometimes useful to make all I/O pins virtual. This example contains procedures to make the process easier.
You might need to see a list of all nodes in a timegroup to verify correct assignments. Use this example to get a list of all nodes in a timegroup.
This example shows a Tcl procedure to get top-level instance names that match a wildcard pattern.
Run a script automatically after compilation, or at any stage during compilation, with the techniques described in this example.
This script automatically creates an archive of your project after compilation and names it based on the compilation end time.
This example shows different ways to include a version number in hardware in your design and have the version number automatically updated every compile.
This script creates a Standard Delay Format Output (.sdo) file with minimum and maximum timing numbers from the two separate minimum and maximum timing SDO files generated by the Quartus II software.
You can create custom report panels in the Compilation Report in the Quartus II GUI. These examples show you how, and present some sample applications.
It can be useful to see a list of settings that you have changed from their default values, especially if changing a setting decreases the performance of your design. This script creates a report panel with non-default global settings in your project.
This example illustrates an easy way to export data from a Quartus II report to a Comma Separated Value
(.csv) file to open in Excel.
When you are optimizing a design, it can be useful to view information about levels of logic between registers. This example generates histogram data you can chart in Excel showing the distribution of paths by levels of logic.
Advanced Classic Timing Analysis
When you use the advanced_timing package, you often need to find the node ID corresponding to a design entry name. Use this procedure to find a node that matches a specified name in the Quartus II timing netlist.
Default Quartus II Tcl commands provide limited support for reporting timing on non-register-to-register paths and do not report every combinational path between endpoints. This advanced script adds those capabilities.