Timing Analyzer Example: Multicycle Exceptions



With the Synopsys® Design Constraint (SDC) command set_multicycle_path, you can specify the number of allowable clock cycles, with respect to either the destination or source clock, for the data to propagate between the source and destination registers. This is useful in the scenario shown in Figure 1.

Figure 1 shows a simple circuit where a multicycle of 2 is required for the destination register reg2. Register reg2 should latch that data every second clock cycle.

Figure 1. Register-to-Register multicycle path.

The SDC commands below constrain the clocks in the above circuit.

#Constrain the base clock

create_clock -period 10.000 [get_ports clk_in]

#Constrain the PLL output clock

create_generated_clock -source inst|inclk[0] -multiply_by 2 \
-name inst|clk[1] inst|clk[1]

#Constrain the input and output ports

set_input_delay -clock clk_in 1.2 [get_ports data_in]
set_input_delay -clock clk_in 1.5 [get_ports async_rst]
set_output_delay -clock clk_in 2 [get_ports data_out]

#Apply a multicycle of 2 to registers reg1 and reg2
#By default the multicycle is relative to the destination clock waveform

set_multicycle_path -setup -end -from [get_pins reg1|clk] -to [get_pins reg2|*] 2

Download example circuit multicycle_exception.qar.

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.