# Timing Analyzer Example: Constraining Generated Clocks

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With the Synopsys® Design Constraint (SDC) command create_generated_clock, you can create arbitrary numbers and depths of generated clocks. This is useful in the following scenarios. See Figures 1 and 2.

Figure 1. Shows a simple circuit where a generated clock is required at the output of register div2reg.

The SDC commands below constrain the clocks in the above circuit.

#Constrain the base clock

-waveform { 0.000 5.000 } \
-name clock_name \
[get_ports clock]

#Constrain the divide by 2 register clock

-name div2clock \
-divide_by 2 \
-master_clock clock_name \
[get_pins div2reg|regout]

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Figure 2. Shows a simple circuit where a generated clock is required at the output of register div2reg.

The SDC commands below constrain the clocks in the above circuit.

#Constrain the base clock

-waveform { 0.000 5.000 } \
-name clock_name \
[get_ports clock]

#Constrain the output clock clock

[get_pins PLL_inst|clk[1]]