VHDL: Counter with Synchronous Reset

BUILT IN - ARTICLE INTRO SECOND COMPONENT

This example describes an 8-bit counter with synchronous reset input design in VHDL.

Figure 1. Counter with synchronous reset top-level diagram.

Table 1. Counter with Synchronous Reset Port Listing

Port Name Type Description
clk Input Clock input
reset Input Synchronous reset
enable Input Count enable
q[7:0] Output 8-bit counter output