The Quartus® II software high-speed differential I/O design example consists of three megafunctions:
- LVDS receiver (altlvds_rx)
- Multiplier (lpm_mult)
- LVDS transmitter (altlvds_tx).
The LVDS receiver, multiplier, and LVDS transmitter modules are created using the Quartus® II software MegaWizard® Plug-In. They are connected as shown in Figure 1, which illustrates the performance of:
- Converting 840 megabits per second (Mbps) serial data into 8-bit parallel data using altlvds_rx
- Multiplication of the two 8-bit parallel data using lpm_mult
- Converting the parallel data coming out of the multiplier into serial data using altlvds_tx
The multiplier will be implemented in a dedicated digital signal processing (DSP) block within the Intel® Stratix® device. The motive behind this example is to show the data conversion. A testbench is created in Verilog and simulated using the ModelSim*-Intel® FPGA tool.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.
Simulating the Design
- Invoke the ModelSim* 5.6c tool.
- Change directory to the location where the simulation files are located.
- Source the script gate_sim.do by using the command: VSIM > do gate_sim.do
Result of multiplication appears after 180 ns.