VHDL: Tri-State Buses

BUILT IN - ARTICLE INTRO SECOND COMPONENT

This example implements 8 tri-state buffers by using a WHEN-ELSE clause in an Architecture Body statement. It does not have a feedback path, and therefore the output pin my_out is designated as OUT, instead of INOUT.

This example is similar to the VHDL: Bidirectional Bus example, except that it does not use a feedback line.

For more information on using this example in your project, go to:


prebus.vhd

LIBRARY IEEE;
    USE ieee.std_logic_1164.ALL;

ENTITY prebus IS
    PORT(
        my_in  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        sel    : IN STD_LOGIC;
        my_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END prebus;

ARCHITECTURE maxpld OF prebus IS
BEGIN
    my_out <= "ZZZZZZZZ"
    WHEN (sel = '1')
    ELSE my_in;
END maxpld;