OpenCL Library feature allows including modules written in Register Transfer Level (RTL) languages, such as VHDL and Verilog, into OpenCL kernels. One or more such RTL modules are packaged into an “OpenCL library” object, which is then passed to aoc as if it were a software library. For more information about OpenCL Library feature, see Intel® FPGA SDK for OpenCL Programming Guide.
Two examples are provided here. The first one contains RTL cores that do not access external memory. This is the preferred way to create OpenCL Library components, as it is easier to design and debug than modules that need to talk to external memory directly.
The second example contains an RTL module that requires Avalon® memory mapped interface to access DDR directly.
The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux* package includes a Makefile and the Windows package includes a Microsoft Visual Studio 2010 project.
The following downloads are provided for this example:
- Example 1: v17.1 x64 Linux package (.tar.gz)
- Example 1: v17.1 x64 Windows package (.zip)
- Example 2: v16.1 x64 Linux package (.tgz)
- Example 2: v16.1 x64 Windows package (.zip)
The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.
Software and Hardware Requirements
This design example requires the following tools:
- Intel FPGA Software v16.1 or later
- Intel FPGA SDK for OpenCL1 v16.1 or later
- On Linux: GNU Make and gcc
- On Windows: Microsoft* Visual Studio 2010
To download the Intel FPGA tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Intel FPGA SDK for OpenCL.
The use of this design is governed by, and subject to, the terms and conditions of the Intel Design Example License Agreement.
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.