AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface (PDF) introduces you to the design flow required to route a hard processor system (HPS) peripheral through the FPGA interface using Qsys and Intel® Quartus® Prime or Quartus® II software. This application note includes a simple tutorial to demonstrate how to map HPS EMAC and I2C peripherals signals to the FPGA interface. It is based on the Golden Hardware Reference Design (GHRD) and provides step-by-step instruction on how to complete the mapping procedure.
The design is provided for the following Intel® FPGA development Kit:
Using This Design Example
To run this example, download the an706-design-files.zip and unzip it to your hard drive. Then, follow the instructions in AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface (PDF).
The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.