Channelizer Design Example

Recommended for:

  • Device: Stratix® V GX

  • Device: v17.1



This example demonstrates an Open Computing Language (OpenCL™) implementation of a channelizer design on Intel® FPGAs. The channelizer combines a polyphase filter bank (PFB) with a fast Fourier transform (FFT) to reduce the effects of spectral leakage on the resulting frequency spectrum.

The core kernels of this benchmark (fft1d, filter, reorder) are designed to operate in a streaming manner, using Intel's channels extension to the OpenCL standard. The channelizer accepts eight real samples streaming into the PFB stage and produces eight complex FFT bins per clock cycle.

Channelizer Performance


  • Sliding window design pattern
  • Single work-item kernels
  • Kernel-to-kernel channels


The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux* package includes a Makefile and the Windows* package includes a Microsoft* Visual Studio 2010 project.

The following downloads are provided for this example:

The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.

Software and Hardware Requirements

This design example requires the following tools:

  • Intel FPGA software v17.1 or later
  • Intel FPGA SDK for OpenCL™ v17.1 or later
  • On Linux: GNU Make and gcc
  • On Windows: Microsoft Visual Studio 2010

To download the Intel® design tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Intel FPGA SDK for OpenCL.

This design example provides precompiled OpenCL device binaries for the following OpenCL boards:

Visualization of Channelizer Output

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at