Fast Passive Parallel Configuration

To meet the continuously increasing demand for faster configuration times, Intel® FPGA devices offer fast passive parallel (FPP) configuration with different data bus widths: 8 bit data width (FPP x8), 16 bit data width (FPP x16), and 32 bit data width (FPP x32). The FPP x16 and FPP x32 schemes are supported only in Stratix® V devices.

For more information, refer to the configuration chapter of the relevant Intel FPGA in the Configuration Handbook.

Configuration Methods

  • Use a processor as an external host
  • Use a MAX® series CPLD as an external host

Embedded Solution

Application Note

AN 386: Using the Parallel Flash Loader with the Quartus® II Software ›

  • Method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the Intel FPGA

Reference Design

MAX Series Configuration Controller Using Flash Memory white paper ›

  • Using a MAX or MAX® II CPLD as a configuration controller to configure Intel FPGAs from flash memory
  • Source code in Verilog and VHDL