Fast Passive Parallel Configuration
Fast passive parallel (FPP) configuration resources provide instructions and tools to help you with your FPGA design.
Configuration Methods
- Use a processor as an external host
- Use a MAX® series CPLD as an external host
Embedded Solution
- Configuring the MicroBlasterTM FPP Software Driver white paper
- Portable software driver used to configure an Intel FPGA via an FPP interface.
- MicroBlaster FPP Software Driver (ZIP) is targeted for embedded fast passive parallel configuration.
User Guide
- Parallel Flash Loader Intel® FPGA IP User Guide
- Method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the Intel FPGA.
Reference Design
- MAX Series Configuration Controller Using Flash Memory white paper
- Using a MAX or MAX® II CPLD as a configuration controller to configure Intel FPGAs from flash memory.
- Flash Memory Configuration Controller Source Code Reference Design (ZIP) in Verilog and VHDL.