Configuration Features
Configuration features supported by Altera FPGAs.
Configuration Features Support provides resources for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, Cyclone® 10, Stratix® V and Arria® V devices.
Get additional support for Agilex™ 7 System Architecture, Agilex™ 5 System Architecture and Agilex™ 3 System Architecture step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.
For other devices, search the Device and Product Support Collections.
Decompression Support
Some FPGAs support configuration data decompression, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compressed bitstream to the FPGA. During configuration, the FPGA decompresses the bitstream in real time and configures its CRAM cells.
Table 1. Design Security Support
Table 1 provides documentation on Design Security Support.
FPGAs can decrypt a configuration bitstream using the advanced encryption standard (AES) algorithm. When using the design security feature, a security key is stored in the FPGA. To successfully configure an FPGA that has the design security feature enabled, you must configure the FPGA with a configuration file that was encrypted using the same security key. Some FPGAs offer both volatile and non-volatile security key storage. The volatile security key storage requires battery back-up but enables the security key to be updated. The non-volatile security key can be stored in non-volatile memory inside the device and does not require battery back-up for storage.
| Documentation | Supported Devices | Description |
|---|---|---|
Agilex™ 7 Agilex™ 5 Agilex™ 3 Stratix® 10 |
Altera® products are designed with dedicated, highly configurable security hardware and firmware. Altera® applies the security development lifecycle across software, firmware, and hardware to develop and maintain more secure products. No product or component can be completely secure. |
|
Arria® 10 Cyclone® 10 Stratix® V Arria® V Cyclone® V Stratix® IV Arria® II |
This application note describes how you can use the design security features in Altera® 40-, 28- and 20-nm FPGAs to protect your designs against unauthorized copying, reverse engineering, and tampering of your configuration files |
|
Stratix® II Stratix® II GX |
When using the Stratix II or Stratix II GX design security feature, the security key is stored in a non-volatile location inside the Stratix II or Stratix II GX device. |
|
| Stratix® III | This aplication note covers, overview of the design security feature, hardware and software requirements, steps for implementing a secure configuration flow, supported configuration schemes, serial flashloader support with encryption enabled, considerations when choosing a configuration scheme, timing parameters with design security feature enabled and United States export controls. |
Table 2. Remote System Upgrade Support
Table 2 provides documentation for remote system upgrade support.
Altera devices have dedicated remote system upgrade circuitry. Soft logic (either the Nios® V embedded processor or user logic) implemented in the device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. This dedicated remote system upgrade circuitry helps to avoid system downtime.
| Documentation | Supported Devices | Description |
|---|---|---|
Arria® 10 Cyclone® 10 GX Cyclone® 10 LP Stratix® V Arria® V Cyclone® V Stratix® IV Cyclone® IV Arria® II |
The Remote Update Altera® FPGA IP core implements a device reconfiguration using dedicated remote system upgrade circuitry available in supported devices. |
|
An 521: Cyclone® III Active Parallel Remote System Upgrade Reference Design |
Cyclone® III | This application note covers these topics overview on remote update mode, reference design functional description, reference design signals, factory image user logic state machine, application image user logic state machine, factory image and application image addressing, system requirements, Cyclone III ap remote system upgrade testing procedure, triggering system reconfiguration, monitoring system parameters using signaltap logic analyzer. |
Table 3. Configuration Features Supported by Altera FPGAs
Table 3 provides a summary of the configuration features supported by Altera device families.
Device |
Decompression Support |
Design Security Support |
Remote System Upgrade Support |
|---|---|---|---|
Agilex™ FPGA and SoC FPGAs |
✓ |
✓ |
✓ |
Stratix® 10 FPGA and SoC FPGAs |
✓ |
✓ |
✓ |
Arria® 10 FPGA and SoC FPGAs |
✓ |
✓ |
✓ |
Cyclone® 10 GX FPGAs |
✓ |
✓ |
✓ |
Cyclone® 10 LP FPGAs |
✓ |
✓ |
✓ |
MAX® 10 FPGAs |
✓ |
✓ |
✓ |
Stratix® V |
✓ |
✓ |
✓ |
Arria® V SoC |
✓ |
✓ |
✓ |
Arria® V |
✓ |
✓ |
✓ |
Cyclone® V SoC |
✓ |
✓ |
✓ |
Cyclone® V |
✓ |
✓ |
✓ |
Stratix® IV |
✓ |
✓ |
✓ |
Cyclone® IV E |
✓ |
- |
✓ |
Cyclone® IV GX |
✓ |
- |
✓ |
Stratix® III |
✓ |
✓ |
✓ |
Cyclone® III LS |
✓ |
✓ |
✓ |
Cyclone® III |
✓ |
- |
✓ |
Arria® II GX |
✓ |
✓ |
✓ |
Cyclone® II |
✓ |
- |
- |