You can perform active parallel (AP) configuration using a supported common flash interface (CFI) parallel flash memory. During AP configuration, the Intel® FPGA device is the host and the parallel flash memory is the agent. Configuration data is transferred to the Intel FPGA device on the DATA[15:0] pins. This configuration data is synchronized to the DCLK input. Configuration data is transferred at a rate of 16 bits per clock cycle. The DCLK frequency driven out by the Intel FPGA device during AP configuration is approximately 40 MHz.
For more information, please refer to the configuration chapter of the relevant Intel FPGA device in the configuration handbook.