Due to an incorrect configuration in the clock divider for the Soft PHY clock in the Baseline GHRD (GHRD 2.0) for the Premium development kit, the Soft PHY Clock frequency is set to run at 50 MHz, preventing the SD Controller from operating in SD modes with a higher frequency than this. The problem is derived from the incorrect value assigned to the clock divider, 4, which, to generate the Soft PHY clock, divides the frequency of the L4 Peripheral clock (200 MHz) by 4. This problem does not affect SD Card boot in the Modular development kit because, in the 25.3 release, the baseline GHRD is only supported in the Premium development kit. This problem does not affect booting from eMMC in any of the Agilex 5 development kits because, in the 25.3 release, the Baseline GHRD does not support this booting mode.
To workaround this problem, you need to modify and rebuild the hardware design provided in the Baseline GHRD. For this, you need to change the value of the Soft PHY clock divider from 4 to 1 in Platform Designer from the HPS Parameters > HPS Clock, Reset, Power > PLL Clocks GUI, as indicated next. With this update, the Soft PHY Clock will be running to 200 MHz, allowing the HPS to operate in SD modes under this new frequency limit.
This problem will be fixed in a future release.