Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may observe below warnings when upgrading any older GTS SDI II IP Design Example with Single Rate (SDI_II Wrapper - (Both base and PHY/ Base only) ) Merging Design (Enable Dual Simplex = 1).
warning check failed!
> warning: combined the following ports to port system_pll_clk in the output netlist for reconfiguration group ds_group_0
> warning: combined the following ports to port system_pll_lock in the output netlist for reconfiguration group ds_group_0
> warning: combined the following ports to port system_pll_clk in the output netlist for reconfiguration group ds_group_0
> warning: combined the following ports to port system_pll_lock in the output netlist for reconfiguration group ds_group_0
To work around this problem when migrating the design from older version of the Quartus® Prime Pro Edition to version 25.3, please update the .qsf file as below.
SDI_II Wrapper (Both Base and PHY)
- set_instance_assignment -name DS_SHARED_CLOCK system_pll_clk -to sdi_tx_inst0|system_pll_clk -entity DS_GROUP_0
- set_instance_assignment -name DS_SHARED_CLOCK system_pll_clk -to sdi_rx_inst0|system_pll_clk -entity DS_GROUP_0
- set_instance_assignment -name DS_SHARED_CLOCK system_pll_lock -to sdi_tx_inst0|system_pll_lock -entity DS_GROUP_0
- set_instance_assignment -name DS_SHARED_CLOCK system_pll_lock -to sdi_rx_inst0|system_pll_lock -entity DS_GROUP_0
SDI_II Wrapper (Base only)
- set_instance_assignment -name DS_SHARED_CLOCK system_pll_clk -to dphy_tx_inst0|i_system_pll_clk[0] -entity DS_GROUP_0
- set_instance_assignment -name DS_SHARED_CLOCK system_pll_clk -to dphy_rx_inst0|i_system_pll_clk[0] -entity DS_GROUP_0
- set_instance_assignment -name DS_SHARED_CLOCK system_pll_lock -to dphy_tx_inst0|i_system_pll_lock[0] -entity DS_GROUP_0
- set_instance_assignment -name DS_SHARED_CLOCK system_pll_lock -to dphy_rx_inst0|i_system_pll_lock[0] -entity DS_GROUP_0
This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.