Article ID: 000102026 Content Type: Errata Last Reviewed: 10/16/2025

Why does the GTS SDI II IP observe a Single Rate (SR) Dual Simplex (DS) port failure when migrating from an older version of the SR DS Design Example to Quartus® Prime Pro Edition Software version 25.1?

Environment

    Intel® Quartus® Prime Pro Edition
    SDI II Intel® FPGA IP
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Description

Due to a problem in the Quartus Prime Pro Edition software version 25.1, you may observe the Dual Simplex(DS) port failure in GTS SDI II IP when migrating an SR DS design generated by a former version to the Quartus Prime Pro Edition software version 25.1. This is because the Dual Simplex port name changes. 

Resolution

To work around this problem, modify the GTS SDI top level file (sdi_ii_agi_demo.sv) in example_design/rtl/ path.  

Example:  

  • SDI II Wrapper = Both Base and PHY 
  • sdi_rx_inst0_auto_rx_cdr_refclk -> rx_cdr_refclk_sdi_rx_inst0 
     
  • SDI II Wrapper = Base only 
  • dphy_rx_inst0_auto_i_rx_cdr_refclk_p -> i_rx_cdr_refclk_p_dphy_rx_inst0 
Additional information

This list of port name changes can be found in this link.

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