In Agilex™ 5 devices with only one transceiver quad (A5E008 or A5E013), if both PCIe* and non-PCIe channels are implemented in the same quad, and the two transceiver reference clock pins are already assigned to drive the TX PLL and CDR for those channels, then no additional transceiver reference clock pin is available to drive the System PLL for the PCIe channel.
The local oscillator can drive the System PLL for the PCIe channel via an HVIO reference clock pin. However, HVIO reference clock pins are released from tristate after the FPGA enters user mode. As a result, the System PLL for the PCIe channel driven by an HVIO reference clock achieves lock only after the FPGA enters user mode, thereby gating PCIe link training and CvP.
For Agilex™ 5 devices configured as PCIe End Points in open systems with a common reference clock topology, CvP is not supported. For PCIe End Points without CvP, the link-up time requirement may not be met.
To work around this problem, use the reference clock pin from the PCIe* host (which drives TX PLL and CDR via a transceiver reference clock pin) to drive the PCIe System PLL as well. The reference clock from the PCIe host must always be available after the PCIe link is up. If the reference clock is disrupted, device reconfiguration is required.
This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.