Due to an inadequate configuration in the Linux* device tree node for the HPS Synopsys* DesignWare APB timers in the Agilex™ 3 FPGA, Agilex™ 5 FPGA, and Agilex™ 7 FPGA devices, the timers remain in reset and fail to initialize during the early driver probe stages. This problem is observed regardless of whether they are enabled through the CONFIG_DW_APB_TIMER=y and CONFIG_DW_APB_TIMER_OF=y configuration options and from the device tree.
The root cause of the problem is that the timer driver is not a regular platform driver, and the current clock configuration in the timer node in the device tree uses a clock manager–dependent clock. This is incorrect because the driver does not support the probe/defer mechanism. As a result, the driver probe is not retried immediately after the clock manager is initialized, and the timer driver remains unavailable during the early boot stages.
To work around this problem, you need to modify the clock configuration in the HPS timer node in the device tree by replacing the current clock reference (generated by the clock manager) with the explicit timer clock frequency value, as shown below:
timer1: timer1@ffc03100 {
compatible = "snps,dw-apb-timer";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffc03100 0x100>;
- clocks = <&clkmgr AGILEX_L4_SP_CLK>; /* Remove this line */
- clock-names = "timer"; /* Remove this line */
+ clock-freq = <400000000>; /* Add this line */
};
This problem is scheduled to be fixed in a future release of the FPGA HPS Embedded Software.