How many IOPLLs are used when implementing Agilex™ 7 FPGA M-Series LVDS SERDES IP in RX DPA-FIFO/Soft-CDR mode and distributing the channels between two sub-banks?

When in DPA-FIFO/Soft-CDR mode, the Agilex™ 7 FPGA M-Series LVDS SERDES IP selects the best clock from the eight fast clock signals generated by the I/O PLL, and it uses it to deserialize the data correctly. These signals are generated using these two modes and cannot be shared between sub-banks. Because of this, when using DPA-FIFO or Soft-CDR mode and distributing the channels between two sub-banks, two IOPLLs are used, one for each sub-bank.

When designing with Agilex™ 7 FPGA M-Series LVDS SERDES IP and using DPA-FIFO or Soft-CDR, please be aware that when distributing the channels between two sub-banks, the IOPLLs of each sub-bank will be used.