Why does the PCIe* link remain at the Polling.Compliance state after reconfiguring the Agilex™ 5 FPGA E-Series 065B Development Kit?

The Agilex™ 5 FPGA Modular Development Kit implements eight lanes on the edge connector. The lower four lanes are used in this setup, while the upper four are properly terminated but unused. The presence of the termination at the upper four unused lanes can lead to complications at the root port during reconfiguration. You might notice that the PCIe* link becomes stuck in the Polling.Compliance state when reconfiguring the Agilex™ 5 FPGA E-Series 065B Development Kit after establishing the PCIe link on certain host systems.

To address this problem, you can either configure the PCIe link width to x4 in the host system BIOS or apply insulating tape to mask the upper four lanes.