Why does the GTS AXI Streaming IP for PCI Express* design example for Agilex™ 5 FPGAs fail to operate and enumerate in hardware when loaded from QSPI on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1)?

Due to a problem in the MAX® 10 FPGAs' power sequence, the SYSPLL input clock is not stable before the configuration process of the Agilex™ 5 FPGAs. You may observe that the Agilex™ 5 FPGA GTS PCIe AXI Streaming design example fails to operate and enumerate in hardware when loaded from QSPI on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1).

You may download the updated POF file for MAX® 10 FPGAs (max10-output-file-1-b.pof), follow the steps below to program the MAX® 10 FPGAs POF file with a USB Micro cable:

1. Set Switch S13-3 to "OFF" and plug in the USB Micro cable between the Dev Kit and the PC.
2. Power on the Dev Kit.
3. Open the Command Prompt in Windows, and run below commands:
   • jtagconfig --setparam 1 JtagClock 16M
   • jtagconfig --setparam 1 JtagClockAutoAdjust 0
   • jtagconfig --setparam 1 InternalMaxSelect 1
4. Open the Quartus® Programmer GUI and program the MAX® 10 FPGAs POF file.
5. Power cycle the Dev Kit.