The total frame range for the Agilex™ 5 FPGA and the Agilex™ 3 FPGA devices is from bit0-bit12 (total 13 bits), while the maximum frame covered in the current Advanced SEU Detection IP, ASD IP, is from bit0-11(total 12 bits). The ASD IP frame range(12 bits) does not cover all the row and frame index combinations for the Agilex™ 5 FPGA and the Agilex™ 3 FPGA devices.
This issue is also affecting the Fault Injection Debugger Tool, FID tool.
As a result, the ASD IP and FID tool might report the incorrect bit position within the frame and/or the combination of row and frame index.
Besides, you might not get an error when you read the Error Message Queue, although you have successfully injected the SEU error.
You cannot insert SEU in the frame range between 1000- 1FFF. Instead, SEU error will be inserted in the frame range from 0- FFF.
However, the SEU detection and correction are still fine for the entire bit and frame.
To inject the SEU error to a pre-defined safe location: insert a safe SEU error with the mailbox command (INSERT_SAFE_SEU_ERROR 0x41) or the FID tool. Then, read the SEU with mailbox command (READ_SEU_ERROR 0x3C) or read the avst_seu_source_data signal of the ASD IP.
Refer to the SEU Error Message Queue Bit Description in the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs and Agilex™ 3 FPGAs and SoCs to decode it.
Note: Do not use READ_SEU_ERROR 0x3C mailbox command if your design contains the Advanced SEU Detection IP.
Request a patch to inject into another location not listed in the pre-defined safe location.
This is scheduled to be fixed in a future release of Intel® Quartus® Prime Pro Edition Software.